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? 2011 semtech corporation power management 1 SC410A 2a ecospeed ? step-down regulator with ldo and power save typical application circuit rev. 1.0 features input voltage 7v to 24v output voltage 0.75v to 7.5v output current up to 2a internal reference + 1% small ceramic capacitors power good pin (open-drain) adaptive on-time control: excellent transient response programmable pseudo-fixed frequency during ccm fault protection features (automatic fault recovery): cycle-by-cycle current limit short circuit protection over and under output voltage protection over-temperature internal soft-start power save and smart psave internal ldo for bias voltage ultra-small lead-free 3 x 3(mm), 10-pin mlpd package weee and rohs compliant and halogen-free applications networking equipment, embedded systems medical equipment, ofce automation instrumentation, portable systems consumer devices such as dtv and set-top boxes pol converters ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? description the SC410A is an integrated, synchronous 2a ecospeed ? step-down regulator. it incorporates semtechs advanced, patented adaptive on-time architecture to achieve best- in-class dynamic performance using point-of-load appli - cations. the input voltage range is 7v to 24v with a programmable output voltage from 0.75v up to 7.5v. the device features an internal ldo and psave mode for high efciency across the output load range. adaptive on-time control provides programmable pseudo-fxed frequency operation in continuous conduc - tion and excellent transient performance. the switching frequency can be set from 200khz to 1mhz, allowing the designer to reduce external lc fltering and minimize light load (standby) losses. additional features include cycle-by-cycle current limit, soft start, output ov protection and over temperature protection. the open-drain pgood pin provides output status. the device is available in a low profle, thermally enhanced mlpd 3 x 3(mm) 10-pin package. sc 410 a en vin ton ldo lx bst v out enable v in fb pgood c in c ldo 2 r ton l 1 c bst c out r top r bot pgood c ldo 1 pgnd agnd www.datasheet.co.kr datasheet pdf - http://www..net/
SC410A 2 pin confguration ordering information top view 1 2 3 4 10 9 8 7 5 6 bst vin lx pgnd en ldo agnd ton pgood fb mlpd;f3fxf3,f10flead ja f=f 40 c/w marking information 410 a yyww xxxx yywwf=fdatefcode xxxxf=flotfnumber device package SC410Amltrt (1)(2) mlpd-10 3 x 3 SC410Aevb evaluation board notes: (1) available in tape and reel only. a reel contains 3,000 devices. (2) lead-free packaging only. device is weee and rohs compliant and halogen-free. www.datasheet.co.kr datasheet pdf - http://www..net/
SC410A 3 absolute maximum ratings lx to gnd (v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +28 vin to pgnd, en to agnd (v) . . . . . . . . . . . . . . . . . -0.3 to +28 vin to ldo (v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0 . 3 bst to lx (v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.0 bst to pgnd (v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +34 ldo to agnd (v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.0 fb, pgood, ton (v) . . . . . . . . . . . . . . . . . . . . -0.3 to ldo +0.3 agnd to pgnd (v) . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +0.3 maximum peak inductor current (a) . . . . . . . . . . . . . . . . . 5 . 5 peak ir refow temperature ( c ) . . . . . . . . . . . . . . . . . . . . . 260 esd protection level (kv) (1) . . . . . . . . . . . . . . . . . . . . . . . . . . 2 . 5 recommended operating conditions supply input voltage ( v ) . . . . . . . . . . . . . . . . . . . . . . . 7 to 24 maximum continuous output current ( a ) . . . . . . . . . . . . . 2 maximum peak inductor current ( a ) . . . . . . . . . . . . . . . . . 5.0 thermal information storage temperature ( c ) . . . . . . . . . . . . . . . . . . -60 to +150 maximum junction temperature ( c ) . . . . . . . . . . . . . . . . 150 operating junction temperature ( c ) . . . . . . . -40 to +125 thermal resistance, junction to ambient (2) ( c/w ) . . . . 40 exceeding the above specifcations may result in permanent damage to the device or device malfunction. operation outside of the parameters specifed in the electrical characteristics section is not recommended. notes: (1) tested according to jedec standard jesd22-a114-b. (2) calculated from package in still air, mounted to 3 x 4.5 (in), 4 layer fr4 pcb with thermal vias under the exposed pad per jesd51 standards. electrical characteristics unless specifed: v in =12v, t a =+25c for typ, -40c to +85c for min and max, t j < 125c, per detailed application circuit parameter conditions min typ max units input supplies internal bias uvlo threshold rising uvlo v th 4 v internal bias uvlo hysteresis 0.3 v vin supply current v en = 0v 225 a i out = 0a (1) 0.8 ma controller fb on-time threshold 0.7425 0.75 0.7575 v frequency programming range see r ton calculation 200 1000 khz fb input bias current fb=5v or 0v -1 +1 a timing on-time continuous mode v in =15v, v out =3v, r ton = 200k? 0.9 1 1.1 s minimum on-time (1) 100 ns minimum of-time (1) 320 ns auto-recovery interval 28 ms www.datasheet.co.kr datasheet pdf - http://www..net/
SC410A 4 parameter conditions min typ max units soft start soft start time (1) delay from pwm switching to output regulation 850 s current sense zero-crossing detector threshold lx - pgnd -10 0 +10 mv power good power good threshold upper limit, v fb > internal 750mv reference 120 %v ref lower limit, v fb < internal 750mv reference 90 pgood delay time (1) between vout at 90% of its regulation value and the pgood signal transitioning to high 1 ms noise immunity delay time (1) 5 s leakage 1 a power good on-resistance 10 ? fault protection output under-voltage fault fb with respect to ref, 8 consecutive switching cycles 75 %v ref output over-voltage fault fb with respect to ref 120 %v ref smart powersave protection threshold fb with respect to ref 110 %v ref ov, uv fault noise immunity delay (1) 5 s over-temperature shutdown (1) 145 c over-temperature shutdown hysterisis (1) 10 c enable logic pwm output enabled (1) 0.8 v en input bias current v en = 5v -10 10 a gate drivers bst switch on resistance 25 ? electrical characteristics (continued) www.datasheet.co.kr datasheet pdf - http://www..net/
SC410A 5 electrical characteristics (continued) parameter conditions min typ max units internal power mosfets current limit inductor valley current limit, vldo=5v 1.5 2 a lx leakage current vin=24v, lx=0v, high side 1 10 a switch resistance high side 215 m? low side 110 non-overlap time (1) 15 ns linear regulator (the ldo is shorted to the bias node, internally) ldo accuracy -4 4 %v ldo ldo current limit short circuit protection, v in = 12v, v ldo <80% of fnal v ldo value 35 ma operating current limit, v in = 12v, v ldo > 80% of fnal v ldo value 100 ldo drop out voltage from v in to v ldo , i ldo = 100ma 0.75 v note: (1) typical value from evb, not ate tested. www.datasheet.co.kr datasheet pdf - http://www..net/
SC410A 6 typical characteristics efciencyfvs.fload 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 10 i out (a dc ) efficiency (%) v in = 9 v v in = 14 v v in = 24 v powerflossfvs.fload v in = 9 v v in = 24 v 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 0.001 0.01 0.1 1 10 i out (a dc ) p loss (w) v in = 14 v loadfregulationfvs.fload v in = 9 v v in = 24 v 4.75 4.8 4.85 4.9 4.95 5 5.05 5.1 5.15 5.2 5.25 0.001 0.01 0.1 1 10 i out (a dc ) v out (v dc ) v in = 14 v frequencyfvs.fload 0 100000 200000 300000 400000 500000 600000 700000 0 0.5 1 1.5 2 i out (a dc ) frequency (hz) outputfvoltagefripplefvs.fload v in = 24 v v in = 14 v v in = 9 v 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0 0.5 1 1.5 2 i out (a dc ) v ripple (v ) v out = 5v v out = 5v v out = 5v v out = 5v, v in = 14v v out = 5v www.datasheet.co.kr datasheet pdf - http://www..net/
SC410A 7 typical characteristics (continued) psaveff0maff time (200s/div) v out = 5v, v in = 14v v out (20mv/div) lx (10v/div) cmmff1aff time (1s/div) v out = 5v, v in = 14v v out (20mv/div) lx (10v/div) start-upffv in ftoggleff time (5ms/div) v out = 5v, v in = 14v, i out = 1a v out (2v/div) lx (10v/div) start-upffenfftoggle time (200s/div) v out (2v/div) lx (10v/div) v out = 5v, v in = 14v, i out = 1a shutdownffv in ftoggleff time (5ms/div) v out (2v/div) lx (10v/div) v out = 5v, v in = 14v, i out = 1a shutdownffenftoggleff time (5ms/div) v out (2mv/div) lx (10v/div) v out = 5v, v in = 14v, i out = 1a www.datasheet.co.kr datasheet pdf - http://www..net/
SC410A 8 typical characteristics (continued) transientfresponseff time (200s/div) v out = 5v, v in = 14v, i out = 1a to 0a to 1a v out (50mv/div) lx (5v/div) overfcurrentff-fshortfcircuit time (20s/div) v out = 5v, v in = 14v v out (5v/div) pgood (5v/div) i l (1v/div) lx (2v/div) enframpff time (200ms/div) v out = 5v, v in = 14v, i out = 1a v out (5v/div) lx (10v/div) enframpf time (200ms/div) v out (5v/div) lx (10v/div) v out = 5v, v in = 14v, i out = 0a v en (5v/div) pgood (5v/div) v en (5v/div) pgood (5v/div) v in fvariationff time (1s/div) v ldo (5v/div) lx (5v/div) v out = 5v, v in = 8v to 0v to 8v, i out = 0a v in (5v/div) v out (5v/div) v in fvariationf-fzoom time (10ms/div) v out (5v/div) lx (5v/div) v out = 5v, i out = 0a v in (5v/div) v ldo (5v/div) www.datasheet.co.kr datasheet pdf - http://www..net/
SC410A 9 detailed application circuit u 1 s c 410 a bst 1 vin 2 lx 3 pgnd 4 en 7 ton 8 agnd 9 ldo 10 fb 6 pgood 5 c bst c top np r ton r top r l np 10 nf c c c out 2 ( 1 ) c out 3 ( 1 ) c out 1 ( 1 ) 2 a max . c l v in c ldo 2 0 . 1 f l 1 r bot c ldo 1 + 7 to + 24 vdc c in ( 1 ) note : ( 1 ) ceramic capacitors v ldo 10 f 0 . 1 f 1 f v out v in r pgood r en c c _ 1 r 8 position as close to ic as possible 0 ? 4 . 7 h 11 . 7 k ? 10 nf 56 . 2 k ? 10 k ? 73 . 2 k ? 180 pf 47 f np np www.datasheet.co.kr datasheet pdf - http://www..net/
SC410A 10 pin descriptions pin # pin name pin function 1 bst bootstrap pin a capacitor is connected between bst and lx to develop the foating voltage for the high-side gate drive. 2 vin power input supply voltage 3 lx switching (phase) node 4 pgnd power ground 5 pgood open-drain power good indicator high impedance indicates power is good. an e xternal pull-up resistor is required. 6 fb feedback input for switching regulator connect to an external resistor divider from the output to pro - gram the output voltage. 7 en enable input for switching regulator pull en high to enable the pwm. connect to agnd to disable the switching regulator. 8 ton on-time set input set the on-time by connecting a series resistor to agnd. 9 agnd analog ground. 10 ldo output for the internal ldo and internal connection to the bias node decoupling capacitors are required to agnd and pgnd regardless of the use of the ldo for external loads. the ldo is enabled regardless of the en pin state. pad thermal pad for heatsinking purposes. (not connected internally) connect to agnd plane using multiple vias. www.datasheet.co.kr datasheet pdf - http://www..net/
SC410A 11 block diagram reference soft start agnd on - time generator pwm control and status pgood gate drive control bst pgnd ton zero cross detector ldo 5 v ldo vin fb comparator lx en 1 10 8 5 7 4 9 r ilim valley current limit ldo ldo lx 2 3 fb 6 v in ilim fb ldo ldo vin www.datasheet.co.kr datasheet pdf - http://www..net/
SC410A 12 synchronous buck converter the SC410A is a step down synchronous buck dc-dc reg - ulator. the device is capable of 2a operation at very high efciency in a tiny 3 x 3-10 pin package. the programma - ble operating frequency range of 200khz C 1mhz enables the user to optimize the design for minimum board space and optimum efciency. the buck regulator employs pseudo-fixed frequency adaptive on-time control. this control method allows fast transient response thereby lowering the size of the power components used in the system. input voltage range the SC410A can operate with a wide input voltage ranging from 7v to 24v. the internal ldo generates a fxed 5v output that provides power for the bias of the SC410A. the ldo can also provide additional power to an external load. psuedo-fxed frequency adaptive on-time control the pwm control method used by the SC410A is pseudo- fxed frequency, adaptive on-time, as shown in figure 1. the ripple voltage generated at the output capacitor esr is divided down by the feedback resistor network and used as a pwm ramp signal. the ripple seen at the fb pin is used to trigger the on-time of the controller. q 1 q 2 l c out esr + c in v out fb threshold v fb v lx v lx ton fb v in figuref1ffpwmfcontrolfmethod,fv out fripple the adaptive on-time is determined by an internal one- shot timer. when the one-shot is triggered by the feed - back ripple, the device sends a single on-time pulse to the high-side mosfet. the pulse period is determined by the output voltage value and v in . the period is proportional to output voltage and inversely proportional to input voltage. the value of the output voltage is obtained by fltering the voltage seen on the lx pin. with this adaptive on-time design, the device automati - cally anticipates the on-time needed to regulate v out for the present v in condition and at the selected frequency. the advantages of adaptive on-time control are: predictable operating frequency during ccm compared to other variable frequency methods. reduced component count by eliminating the e r r o r a m p l i f i e r a n d c o m p e n s a t i o n components. reduced component count by removing the need to sense and control inductor current. fast transient response the response time is controlled by a fast comparator instead of a typically slow error amplifer. reduced output capacitance due to fast tran - sient response one-shot timer and operating frequency the one-shot timer operates as shown in figure 2. the feedback comparator output goes high when v fb is less than the internal 750mv reference. this feeds into the gate drive and turns on the high-side mosfet, and also starts the one-shot timer. the one-shot timer uses an internal comparator, timing capacitor, and a low pass filter (lpf) which regenerates v out from lx. one compar - ator input is connected to the filtered lx voltage, the other input is connected to the capacitor. when the on- time begins, the internal capacitor charges from zero volts through a current which is proportional to v in . when the capacitor voltage reaches v out , the on-time is com - pleted and the high-side mosfet turns of. ? ? ? ? ? applications information www.datasheet.co.kr datasheet pdf - http://www..net/
SC410A 13 applications information (continued) pwm one - shot timer time = k x ( v out / v in ) v in fb ref . q 1 q 2 l c out v in esr v lx fb hi - side and lo - side gate drivers r ton + - v out + lpf q r s v lx _ filter v lx _ filter figuref2ffon-timefgeneration this method automatically produces an on-time that is proportional to v out and inversely proportional to v in . under steady-state operating conditions in continuous conduction mode, the switching frequency can be deter - mined from the on-time by the following equation. in on out sw v t v f u the SC410A uses an external resistor to set the on-time which indirectly sets the frequency. the on-time can be programmed to provide operating frequencies from 200khz to 1mhz using a resistor between the ton pin and ground. the resistor value is selected by the follow - ing equation. 2 . 1 v v 400 f 25pf 1 r out in sw ton u ? ? 1 ? u : u the maximum r ton value allowed is shown by the follow - ing equation. a 5 . 1 10 v r min _ in max _ ton p u immediately after the on-time, the dl (the drive signal for the low side fet) output drives high to turn on the low- side mosfet. dl has a minimum high time of ~320ns, after which dl continues to stay high until one of the fol - lowing occurs: v fb falls below the 750mv reference the zero cross detector senses that the voltage on the lx node is below ground. psave is acti - vated 8 periods after the zero cross is detected. ? ? v out voltage selection the switcher output voltage is regulated by comparing v out as seen through a resistor divider at the fb pin to the internal 750mv reference voltage, see figure 3. r 1 to fb pin r 2 v out figuref3ffoutputfvoltagefselection note that this control method regulates the valley of the output ripple voltage, not the dc value. the dc output voltage v out is ofset by the output ripple according to the following equation. ? 1 ? ? ? 1 ? u 2 v r r 1 75 . 0 v ripple 2 1 out enable input the en input is used to enable or disable the switching regulator. the ldo remains on regardless of the state of the en pin. when en is low (grounded), the switching regulator is disabled. when disabled, the output power switches are tri-stated. when en is higher than 0.8v, switching regulator is activated. continuous mode operation the SC410A operates in ccm (continuous conduction mode) at larger load currents when the load is greater than or equal to half of the inductor ripple current (figure 4). in this mode one of the power mosfets is always on, with no intentional dead time other than to avoid cross- conduction. this mode of operation results in uniform frequency. www.datasheet.co.kr datasheet pdf - http://www..net/
SC410A 14 fb ripple voltage ( v fb ) fb threshold dl dh inductor current dc load current dh on - time is triggered when v fb reaches the fb threshold . ( 750 mv ) on - time ( t on ) dl drives high when on - time is completed . dl remains high until v fb falls to the fb threshold . figuref4ffcontinuousfmodefoperation power-save mode operation the SC410A provides power-save operation at light loads with no minimum operating frequency. with power-save enabled, the internal zero crossing comparator monitors the inductor current via the voltage across the low-side mosfet during the of-time. if the inductor current falls to zero for 8 consecutive switching cycles, the controller enters power-save operation. it will turn of the low-side mosfet on each subsequent cycle provided that the current crosses zero. at this time both mosfets remain of until v fb drops to the 750mv threshold. because the mosfets are of, the load is supplied by the output capaci - tor. if the inductor current does not reach zero on any switching cycle, the controller immediately exits power- save and returns to forced continuous mode. figure 6 shows power-save operation at light loads. applications information (continued) fb ripple voltage ( v fb ) fb threshold dl dh inductor current zero ( 0 a ) dh on - time is triggered when v fb reaches the fb threshold . ( 750 mv ) on - time ( t on ) dl drives high when on - time is completed . dl remains high until inductor current reaches zero . dead time varies according to load figuref5ffpowerfsavefoperation smart power save protection active loads may leak current from a higher voltage into the switcher output. under light load conditions with power save enabled, this can force v out to slowly rise and reach the over-voltage threshold, resulting in a hard shut - down. smart power save prevents this condition. when the fb voltage exceeds 10% above nominal (exceeds 825mv), the device immediately disables power-save, and dl drives high to turn on the low-side mosfet. this draws current from v out through the inductor and causes v out to fall. when v fb drops back to the 750mv trip point, a normal t on switching cycle begins. this method pre - vents a hard ovp shutdown and also cycles energy from v out back to v in . figure 6 shows typical waveforms for the smart power save feature. www.datasheet.co.kr datasheet pdf - http://www..net/
SC410A 15 applications information (continued) fb threshold high - side drive ( dh ) low - side drive ( dl ) v out drifts up to due to leakage current flowing into c out dh and dl off dl turns on when smart psave threshold is reached smart power save threshold ( 825 mv ) dl turns off when fb threshold is reached single dh on - time pulse after dl turn - off v out discharges via inductor and low - side mosfet normal dl pulse after dh on - time pulse normal v out ripple figuref6ffsmartfpowerfsave current limit protection programmable current limiting is accomplished by using the rds on of the lower mosfet for current sensing. the current limit is set by an internal resistor r ilim . the resistor connects from an ilim node to the lx node which is also the drain of the low-side mosfet. when the low-side mosfet is on, an internal ~10 a current fows from the ilim node and through the r ilim resistor, creating a voltage drop across the resistor. while the low-side mosfet is on, the inductor current fows through it and creates a voltage across the rds on . the voltage across the mosfet is nega - tive with respect to ground. if this mosfet voltage drop exceeds the voltage across r ilim , the voltage at the ilim node will be negative and current limit will activate. the current limit then keeps the low-side mosfet on and will not allow another high-side on-time, until the current in the low-side mosfet reduces enough to bring the ilim voltage back up to zero. this method regulates the inductor valley current at the level shown by ilim in figure 7. time i peak i load i lim i n d u c t o r c u r r e n t figuref7ffvalleyfcurrentflimit in the SC410A, the valley current limit is set to 2a. this results in a peak inductor current of 2a plus the peak-to- peak ripple current. in this situation, the average (load) current through the inductor is 2a plus one-half the peak- to-peak ripple current. the internal 10 a current source is temperature compen - sated at 2500ppm in order to provide tracking with the rds on . peak inductor current the peak current through the inductor and switching fets must be less than 5a. the only way to meet this require - ment is to select the switching frequency and inductor value such that the peak inductor current is less than or equal to 5a when the trough of the inductor current is 2a. soft start of pwm regulator soft start is achieved in the pwm regulator by using an internal voltage ramp as the reference for the fb com - parator. the voltage ramp is generated using an internal charge pump which drives the reference from zero to 750mv in ~1.8mv increments, using an internal ~500khz oscillator. when the ramp voltage reaches 750mv, the ramp is ignored and the fb comparator switches over to a fixed 750mv threshold. during soft start the output voltage tracks the internal ramp, which limits the start-up inrush current and provides a controlled soft start profle for a wide range of applications. typical soft start ramp time is 850 s. during soft start the regulator turns off the low-side mosfet on any cycle if the inductor current falls to zero. this prevents negative inductor current, allowing the device to start into a pre-biased output. power good output the pgood (power good) output is an open-drain output which requires a pull-up resistor. when the output voltage is 10% below the nominal voltage, pgood is pulled low. it is held low until the output voltage returns to the nominal voltage. pgood is held low during soft start and activated approximately 1ms after v out reaches regulation. www.datasheet.co.kr datasheet pdf - http://www..net/
SC410A 16 applications information (continued) pgood will transition low if the v fb pin exceeds +20% of nominal, which is also the over-voltage shutdown thresh - old (900mv). output over-voltage protection ovp (over-voltage protection) becomes active as soon as the device is enabled. the threshold is set at 750mv + 20% (900mv). when v fb exceeds the ovp threshold, the output goes to a tri-state with both fets disabled, the pwm is dis - abled and enters automatic fault recovery. there is a 5s delay built into the ovp detector to prevent false transi - tions. pgood is also low during an ovp event. output under-voltage protection when v fb falls to 75% of its nominal voltage (falls to 562.5mv) for eight consecutive clock cycles, the switcher is shut of and the dh and dl drives are pulled low to turn off the mosfets. the controller is disabled and enters automatic recovery. over-temperature protection if the temperature rises to 145 c the device will enter automatic fault recovery after the temperature falls down by 10c . automatic fault recovery the SC410A includes an automatic recovery feature (hiccup mode upon fault). if the switcher output is shut - down due to a fault condition, the device will remain of for 28 ms and there is no mosfet switching. then the normal soft-start cycle is implemented and the mosfets will start a switching cycle. switching continues until the soft-start delay time is reached. if the switcher output is still in a fault condition, the switcher will again shut down and wait another 28 ms before attempting the next soft- start. the long delay between soft-start cycles reduces average power loss in the power components. see figure 8 for an illustration of the auto recovery due to input uvlo. vin vout gate signal for the high side fet vldo vout uvp auto - recovery cycles switching stops due to uvp at the output switching continues due to the output going above the uvp point during the soft - start time of this auto - recovery cycle . vdd uvlo = 4 v no auto - recovery due to internal vdd uvlo figuref8ffautofrecoveryfdueftofinputfuvlo v ldo uvlo, and por uvlo (under-voltage lock-out) circuitry inhibits switch - ing and tri-states the power fets until v ldo rises above 4.0v. an internal por (power-on reset) occurs when v ldo exceeds 4.0v, which resets the fault latch and soft start counter to begin the soft start cycle. the SC410A then begins a soft start cycle. the pwm will shut of if v ldo falls below 3.7v. internal ldo regulator the SC410A has an internal regulator that supplies the bias voltage for the pwm controller. this ldo can also supply an additional external current for an external load through the ldo pin. when activated, the ldo checks the status of the follow - ing signals to ensure proper operation can be maintained. en pin v ldo output voltage vin input voltage while the en pin is above 0.5v, the ldo will be activated. while the v ldo output voltage remains below 4v (80% of the fnal ldo voltage), the ldo short-cicuit protection is enabled and limits the current to about 35ma. after the v ldo exceeds 4.0v, then the ldo operates in its normal regulation mode where the current is limited to about 100ma (see figure 9). 1. 2. 3. www.datasheet.co.kr datasheet pdf - http://www..net/
SC410A 17 applications information (continued) 80 % of v ldo final v ldo final sort - circuit protection @ ~ 35 ma voltage regulating with ~ 100 ma current limit figuref9ffldofstart-up design procedure when designing a switch mode supply the input voltage range, load current, switching frequency, and inductor ripple current must be specifed. the maximum input voltage (v inmax ) is the highest speci - fed input voltage. the minimum input voltage ( v inmin ) is determined by the lowest input voltage after evaluating the voltage drops due to connectors, fuses, switches, and pcb traces. the following parameters defne the design. nominal output voltage (v out ) static or dc output tolerance transient response maximum load current (i out ) the two values of load current to evaluate are continuous load current and peak load current. continuous load current relates to thermal stresses which drive the selec - tion of the inductor and input capacitors. peak load current determines instantaneous component stresses and flter - ing requirements such as inductor saturation, output capacitors, and design of the current limit circuit. the following values are used in this design example. v in = 14v + 10% v out = 5v + 2.5% f sw = 600khz load = 1a maximum frequency selection selection of the switching frequency requires making a trade-of between the size and cost of the external flter ? ? ? ? ? ? ? ? components (inductor and output capacitor) and the power conversion efciency. the desired switching frequency is 600khz which results from using components selected for optimum size and cost. a resistor (r ton ) is used to program the on-time (indirectly setting the frequency) using the following equation. 2 . 1 v v 400 f 25pf 1 r out in sw ton u ? ? 1 ? u : u to select r ton , use the maximum value for v in , and for t on use the value associated with maximum v in . sw inmax out on f v v t u t on = 541 ns at 15.4v in , 5v out , 600khz substituting for r ton results in the following solution. r ton = 78.7k?, use r ton = 78.7k? inductor selection in order to determine the inductance, the ripple current must frst be defned. low inductor values result in smaller size but create higher ripple current which can reduce efciency. higher inductor values will reduce the ripple current/voltage and for a given dc resistance are more efcient. however, larger inductance translates directly into larger packages and higher cost. cost, size, output ripple, and efciency are all used in the selection process. the ripple current will also set the boundary for power- save operation. the switching will typically enter power- save mode when the load current decreases to 1/2 of the ripple current. for example, if ripple current is 2a then power-save operation will typically start for loads less than 1a. if ripple current is set at 40% of maximum load current, then power-save will start for loads less than 20% of maximum current. during the dh on-time, voltage across the inductor is (v in - v out ). the equation for determining inductance is shown next. ripple on out in i t ) v v ( l u www.datasheet.co.kr datasheet pdf - http://www..net/
SC410A 18 applications information (continued) example in this example, the inductor ripple current is set equal to 100% of the maximum load current. therefore ripple current will be 1a. to find the minimum inductance needed, use the v in and t on values that correspond to v in . + $ qv 9 9 / p u a standard value of 4.7h is selected. this gives a maximum i ripple of 1.197a. the peak ripple can be calcu - lated by the equation, below where l tol is assumed to be an inductor tolerance of 20%. i ripple_peak = i ripple_max x (1 + l tol ) = 1.497a note that the inductor must be rated for the maximum dc load current plus 1/2 of the ripple current. i lsat_min = i ripple_peak x 0.5 + i out = 1.748a the ripple current under minimum v in conditions is also checked using the following equations. qv qv 9 9 5 s) w ,10, 1 28 7 721 9,10,1 b 21 u u l t ) v v ( i on out in ripple u $ + qv 9 9 , 9,10,1 b 5,33/ ( p u capacitor selection the output capacitors are chosen based on required esr and capacitance. the maximum esr requirement is con - trolled by the output ripple requirement and the dc toler - ance. the output voltage has a dc value that is equal to the valley of the output ripple plus 1/2 of the peak-to-peak ripple. change in the output ripple voltage will lead to a change in dc voltage at the output. the design goal is for the output voltage regulation to be 2.5% under static conditions. the internal 750mv refer - ence tolerance is 1%. assuming a 1% tolerance from the fb resistor divider, this allows 0.5% tolerance due to v out ripple. since this 0.5% error comes from 1/2 of the ripple voltage, the allowable ripple is 1%, or 50mv for a 5v output. the maximum ripple current of 1.497a creates a ripple voltage across the esr. the maximum esr value allowed is shown by the following equations. $ p9 , 9 (65 5,33/(0$; 5,33/ ( 0$; u esr max = 67 m ? the output capacitance is chosen to meet transient requirements. a worst-case load release, from maximum load to no load at the exact moment when inductor current is at the peak, determines the required capaci - tance. if the load release is instantaneous (load changes from maximum to zero in < 1s), the output capacitor must absorb all the inductors stored energy. this will cause a peak voltage on the capacitor according to the following equation. 2 out 2 peak 2 peak _ ripple out tol min v v i 2 1 i l 1 l cout ? 1 ? u u assuming a peak voltage v peak of 5.05 (50mv rise upon load release), and a 1a load release, the required capaci - tance is shown by the next equation. 0, 1 9 9 $ $ + &287 ? 1 ? u p cout min = 34f if the load release is relatively slow, the output capacitance can be reduced. at heavy loads during normal switching, when the fb pin is above the 750mv reference, the dl output is high and the low-side mosfet is on. during this time, the voltage across the inductor is approximately v out . this causes a down-slope or falling di/dt in the inductor. if the load di/dt is not much faster than the di/dt in the inductor, then the inductor current will tend to track the falling load current. this will reduce the excess inductive energy that must be absorbed by the output capacitor, therefore a smaller capacitance can be used. www.datasheet.co.kr datasheet pdf - http://www..net/
SC410A 19 applications information (continued) the following can be used to calculate the needed capaci - tance for a given di load /dt. peak inductor current is shown by the next equation. i lpk = i max + 1/2 x i ripplemax i lpk = 1a + 1/2 x 1.497a = 1.748a dt dl current load of change of rate load i max = maximum load release = 1a out pk load max out lpk tol lpk out v v 2 dt l d i v i l 1 l i c u u u u example s a dt dl load p 1 1 this causes the output current to move from 1a to 0a in 1s, giving the minimum output capacitance requirement shown in the following equation. v v s a a v a h a c out 5 05 . 5 2 1 1 1 5 748 . 1 % 20 1 7 . 4 748 . 1 u u u p p c out = 17f note that c out is much smaller in this example, 17f com - pared to 34f based on a worst-case load release. to meet the worst case design criteria of minimum 34f, select a capacitor rated at 47f. stability considerations unstable operation is possible with adaptive on-time con - trollers, and usually takes the form of double-pulsing or esr loop instability. double-pulsing occurs due to switching noise seen at the fb input or because the fb ripple voltage is too low. this causes the fb comparator to trigger prematurely after the minimum of-time has expired. in extreme cases the noise can cause three or more successive on-times. double- pulsing will result in higher ripple voltage at the output, but in most applications it will not afect operation. this form of instability can usually be avoided by providing the fb pin with a smooth, clean ripple signal that is at least 10mvp-p, which may dictate the need to increase the esr of the output capacitors. it is also imperative to provide a proper pcb layout. an alternate method to eliminate doubling-pulsing is to add a small (~ 10pf) capacitor across the upper feedback resistor, as shown in figure 10. this capacitor should be left unpopulated unless it can be confrmed that double- pulsing exists. adding the c top capacitor will couple more ripple into fb to help eliminate the problem. an optional connection on the pcb should be provided for this capacitor. v out to fb pin r 2 r 1 c top figuref10ffcapacitorfcouplingftoffbfpin esr loop instability is caused by insufficient esr. the details of this stability issue are discussed in the esr requirements section. the best method for checking sta - bility is to apply a zero-to-full load transient and observe the output voltage ripple envelope for overshoot and ringing. ringing for more than one cycle after the initial step is an indication that the esr should be increased. one simple method of solving this problem is to add trace resistance in the high current output path. a side efect of adding trace resistance is a decrease in load regulation. esr requirements a minimum esr is required for two reasons. the first reason is to generate enough output ripple voltage to provide 10mvp-p at the fb pin (after the resistor divider) to avoid double-pulsing. the second reason is to prevent instability due to insuf - cient esr. the on-time control regulates the valley of the www.datasheet.co.kr datasheet pdf - http://www..net/
SC410A 20 applications information (continued) output ripple voltage. this ripple voltage is the sum of the two voltages. one is the ripple generated by the esr, the other is the ripple due to capacitive charging and dis - charging during the switching cycle. for most applica - tions, the total output ripple voltage is dominated by the output capacitors, typically sp or poscap devices. for stability the esr zero of the output capacitor should be lower than approximately one-third the switching fre - quency. the formula for minimum esr is shown by the following equation. sw out min f c 2 3 sr e u u s u using ceramic output capacitors when applications use ceramic output capacitors, the esr is normally too small to meet the previously stated esr criteria. in these applications it is necessary to add a small signal injection network as shown in figure 11. in this network r l and c l filter the lx switching waveform to generate an in-phase ripple voltage comparable to the ripple seen on higher esr capacitors. c c is a coupling capacitor used to ac couple the generated ripple onto the fb pin. r 1 r 2 fb pin c c c out l low - side high - side c l r l figuref11ffsignalfinjectionfcircuit the values of r l , c l , and c c are dependent on the condi - tions of the specifc application such as v in , v out , f sw and i out . select a value for c l , like 10nf. using c l , calculate r l as shown in the following equation: dcr c l r l l u where l is the inductor value and dcr is the resistance of the inductor. the value for c c can be between c c_min and c c_max . eq on min _ c r t c eq max _ c r t c where t = 1/f sw and r eq is represented by the following equation. top bottom top bottom eq r r r r r u it is benefcial to use the smallest value of c c that provides stability and enough voltage ripple at feedback. larger values of c c may negatively affect the load regulation performance. output voltage dropout the output voltage adjustable range for continuous-con - duction operation is limited by the fxed 320ns (typical) minimum of-time. when working with low input volt - ages, the duty-factor limit must be calculated using worst- case values for on and of times. the duty-factor limitation is shown by the next equation. ) max ( off ) min ( on ) min ( on t t t duty the inductor resistance and mosfet on-state voltage drops must be included when performing worst-case dropout duty-factor calculations. www.datasheet.co.kr datasheet pdf - http://www..net/
SC410A 21 applications information (continued) system dc accuracy v out controller three factors afect v out accuracy: the trip point of the fb error comparator, the ripple voltage variation with line and load, and the external resistor tolerance. the error comparator ofset is trimmed so that under static condi - tions it trips when the feedback pin is 750mv, + 1%. the on-time pulse from the SC410A in the design example is calculated to give a pseudo-fxed frequency of 500khz. some frequency variation with line and load is expected. this variation changes the output ripple voltage. because adaptive on-time converters regulate to the valley of the output ripple, ? of the output ripple appears as a dc regu - lation error. to compensate for valley regulation, it may be desirable to use passive droop. take the feedback directly from the output side of the inductor and place a small amount of trace resistance between the inductor and output capaci - tor. this trace resistance should be optimized so that at full load the output droops to near the lower regulation limit. passive droop minimizes the required output capaci - tance because the voltage excursions due to load steps are reduced as seen at the load. the use of 1% feedback resistors may result in up to an additional 1% error. if tighter dc accuracy is required, resistors with lower tolerances should be used. the output inductor value may change with current. this will change the output ripple and therefore will have a minor efect on the dc output voltage. the output esr also afects the output ripple and thus has a minor efect on the dc output voltage. switching frequency variation the switching frequency will vary depending on line and load conditions. the line variations are a result of fxed propagation delays in the on-time one-shot, as well as unavoidable delays in the power fet switching. as v in increases, these factors make the actual dh on-time slightly longer than the ideal on-time. the net efect is that frequency tends to fall slightly with increasing input voltage. the switching frequency also varies with load current as a result of the power losses in the mosfets and the induc - tor. for a conventional pwm constant-frequency con - verter, as load increases the duty cycle also increases slightly to compensate for ir and switching losses in the mosfets and inductor. an adaptive on-time converter must also compensate for the same losses by increasing the effective duty cycle (more time is spent drawing energy from v in as losses increase). the on-time is essen - tially constant for a given v out and v in combination, to ofset the losses the of-time will tend to reduce slightly as load increases. the net efect is that switching frequency increases slightly with increasing load. www.datasheet.co.kr datasheet pdf - http://www..net/
SC410A 22 pcb layout guidelines the optimum layout for the SC410A is shown in figure 12. this layout shows an integrated fet buck regulator with a maximum current of 2a. the total pcb area is approxi - mately 19.1mm x 11.3mm. critical layout guidelines the following critical layout guidelines must be followed to ensure proper performance of the device. ic decoupling capacitors pgnd plane agnd island fb and other analog control signals bst and lx capacitors and current loops ic decoupling capacitors a 0.1 f capacitor must be located as close as possible to the ic and directly connected to pins 10 (ldo) and 9 (agnd). all other decoupling capacitors must be located as close as possible to the ic. ? ? ? ? ? ? ? ? figuref12ffpcbflayout SC410A lx connection using a via fb node pgnd vesr node pgnd plane pgnd requires its own copper plane with no other signal traces routed on it. copper planes, multiple vias, and wide traces are needed to connect pgnd to input capacitors, output capacitors, and the pgnd pins on the ic. the pgnd copper area between the input capacitors, output capacitors, and pgnd pins must be as small as and as compact as possible to reduce the area of the pcb that is exposed to noise due to current fow on this node. connect pgnd to agnd with a short trace or 0 ? resistor. this connection should be as close to the ic as possible. agnd island agnd should have its own island of copper with no other signal traces routed on this layer that connects the agnd pins and pad of the ic to the analog control components. all of the components for the analog control cir - cuitry should be located so that the connections to agnd are done by wide copper traces or vias down to agnd. ? ? ? ? ? ? www.datasheet.co.kr datasheet pdf - http://www..net/
SC410A 23 connect pgnd to agnd with a short trace or 0 ? resistor. this connection should be as close to the ic as possible. fb and other analog control signals the connection from the v out power to the analog control circuitry must be routed from the output capacitors and located on a quiet layer. the traces between v out and the analog control circuitry (agnd, and fb pins) must be as short as possible. the traces must also be routed away from noise sources, such as bst, lx, vin, and pgnd between the input capacitors, output capacitors, and the ic. the ton node must be as short as possible to ensure the best accuracy for the on time. the feedback components for the switcher need to be as close to the fb pin of the ic as possible to reduce the possibility of noise corrupting these analog signals. ? ? ? ? ? bst and lx lx and bst are very noisy nodes and must be carefully routed to minimized the pcb area that is exposed to these signals. the connections for the boost capacitor between the ic and lx must be short and directly connected to the lx (pin 3). the lx node between the ic and the inductor should be wide enough to handle the inductor current and short enough to eliminate the pos - sibility of lx noise corrupting other signals. capacitors and current loops the current loops between the input capacitors, the ic, the inductor, and the output capacitors must be as close as possible to each other to reduce ir drop across copper planes and traces. all bypass and output capacitors must be con - nected as close as possible to their respective pin on the ic. ? ? ? ? ? applications information (continued) www.datasheet.co.kr datasheet pdf - http://www..net/
SC410A 24 notes: controlling dimensions are in millimeters (angles in degrees). coplanarity applies to the exposed pad as well as terminals. 2. 1. .003 .008 10 .010 - .000 .031 (.008) 0.08 0.25 10 .012 0.20 .039 - .002 - 0.00 0.80 0.30 - 0.05 1.00 (0.20) .004 0.10 0.50 bsc .020 bsc 0.45 .018 .022 .020 0.50 0.55 aaa c seating plane a bbb c a b b e c .114 .118 .122 2.90 3.00 3.10 - - - - (laser mark) indicator pin 1 1 n 2 min aaa bbb b e l n d e1 a1 a2 a dim millimeters nom dimensions max nom inches min max .057 .059 .061 1.45 1.50 1.55 d e a1 a2 d/2 d1 .087 .089 .091 2.20 2.25 2.30 e .114 .118 .122 2.90 3.00 3.10 a d1 e1 e/2 bxn lxn outline drawing mlpd-10 3x3 www.datasheet.co.kr datasheet pdf - http://www..net/
SC410A 25 controlling dimensions are in millimeters (angles in degrees). dimensions inches c (.112) failure to do so may compromise the thermal and/or functional performance of the device. shall be connected to a system ground plane. thermal vias in the land pattern of the exposed pad this land pattern is for reference purposes only. consult your manufacturing group to ensure your company's manufacturing guidelines are met. notes: 3. 2. 1. x z y k p h g .012 .033 .146 .079 .020 .059 .089 dim (2.85) 0.30 0.85 3.70 2.00 0.50 1.50 2.25 millimeters x p g y z (c) h k land pattern mlpd-10 3x3 www.datasheet.co.kr datasheet pdf - http://www..net/
semtech corporation power management products division 200 flynn road, camarillo, ca 93012 phone: (805) 498-2111 fax: (805) 498-3804 www.semtech.com contact information SC410A 26 ? semtech 2011 all rights reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any conse - quence of its use. publication thereof does not convey nor imply any license under patent or other industrial or intellec - tual property rights. semtech assumes no responsibility or liability whatsoever for any failure or unexpected operation resulting from misuse, neglect improper installation, repair or improper handling or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specifed maximum ratings or operation outside the specifed range. semtech products are not designed, intended, authorized or warranted to be suitable for use in life- support applications, devices or systems or other critical applications. inclusion of semtech products in such applications is understood to be undertaken solely at the customers own risk. should a customer purchase or use semtech products for any such unauthorized application, the customer shall indemnify and hold semtech and its ofcers, employees, subsidiaries, afliates, and distributors harmless against all claims, costs damages and attorney fees which could arise. notice: all referenced brands, product names, service names and trademarks are the property of their respective owners. www.datasheet.co.kr datasheet pdf - http://www..net/

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